RTEworks Services

Professional engineering services for automotive software teams.

Senior AUTOSAR engineers, embedded specialists, ASPICE practitioners, ISO 26262 safety engineers, and AI workflow designers on staff. We work with OEMs and Tier-1 suppliers on the pieces of the lifecycle that no one builds well in-house: CI/CD with MISRA C / C++ enforcement on generated and hand-written production code, ECU bring-up, ASIL-rated safety cases, process maturity audits, and the migration paths that actually ship to production.

01 AUTOSAR CI/CD 02 ASPICE compliance 03 ISO 26262 / functional safety 04 AUTOSAR architecture & migration 05 AI for automotive workflows 06 Embedded engineering

01 AUTOSAR CI/CD

Your team ships ARXML changes, hand-written application code, and generated RTE / BSW code through pull requests, gets static analysis, semantic review, and coverage gates automatically, and produces release-ready ECU artifacts at the push of a tag. No more manual integration weeks. No more midnight builds the night before audit.

What we do

  • End-to-end pipeline design across Git host, build system, test infrastructure, and release tooling
  • Static analysis integration: MISRA C / MISRA C++, AUTOSAR C++14 guidelines, LDRA, Coverity, PolySpace, Klocwork, and Simulink Model Advisor. Rules applied uniformly to hand-written application code and generated RTE / BSW code, with documented deviations where the standard demands it
  • Unit and integration test orchestration: VectorCAST, Tessy, BTC EmbeddedPlatform, Simulink Test, MicroMax (DanLaw), Google Test, CppUTest. Coverage gates including MC/DC for ASIL-D paths
  • SIL and HIL pipelines integrated into the same CI run, not bolted on after
  • Semantic ARXML validation gates in CI (custom rule sets or our Manifold engine)
  • Reproducible builds for AUTOSAR Classic and Adaptive toolchains
  • Tool qualification per ISO 26262 (TCL1, TCL2, TCL3) for the tools in your pipeline that need it
  • Automated release artifact generation: signed binaries, ASPICE-aligned evidence packs, audit trails
  • Multi-tool integration: SystemDesk, DaVinci, ISOLAR, EB tresos, Vector toolchain
  • Per-team training so your engineers own the pipeline after we leave

02 ASPICE compliance

Your next ASPICE assessment goes from "frantic three-week prep" to "export the evidence pack from our existing system." Process designs that professional automotive engineers can actually follow during a real release.

What we do

  • Process design for SWE.1 through SWE.6, plus SYS lifecycle and SUP processes
  • Targeted at ASPICE CL2 or CL3 depending on your customer's gate
  • Traceability tooling design across requirements → architecture → code → test, integrated with Polarion, IBM DOORS, Codebeamer, or Reqtify
  • Evidence generation automation aligned with ASPICE 4.0 base practices (no more manual Word doc updates)
  • Mock assessment with assessor-style probes against your current state
  • Assessor coaching for your team going into the real engagement

03 ISO 26262 / functional safety

An ISO 26262 safety case your professional engineers wrote, your safety manager believes, and your assessor will sign. Traceability that lives in your tooling, not in a spreadsheet someone updates the night before audit.

What we do

  • HARA (hazard analysis and risk assessment) facilitation and review
  • Safety goal decomposition into technical safety requirements, ASIL A through D
  • Functional safety concept and technical safety concept authorship
  • Requirement-to-test traceability against ASIL targets, integrated with your release pipeline
  • Safety analysis (FMEDA, FTA, DFA) on your real architecture
  • ISO 26262 evidence pack generation; MISRA C / MISRA C++ enforcement on safety-relevant production code, including generated RTE and BSW code paths that ship on the ECU
  • ISO 21448 SOTIF and ISO 21434 cybersecurity overlap where your program needs it

04 AUTOSAR architecture & migration

A Classic-to-Adaptive migration path your senior engineers signed off on. Composition designs that make sense at scale. SWC reviews from industry experts that catch the problems before they cost six months of integration.

What we do

  • Classic ↔ Adaptive migration scoping with realistic timelines for your team size
  • SDV / zonal ECU architecture design for next-gen platforms, including ECU consolidation, function redistribution, and signal routing across the zonal fabric
  • Composition refactoring: collapsing overgrown SWCs, splitting monoliths
  • ARXML element-level review with senior-engineer-grade feedback
  • Migration tooling design (often including AI-assisted mapping with Manifold)
  • ASIL-decomposition planning for safety-relevant SWCs migrating to Adaptive
  • Architecture review board (ARB) facilitation when your team needs structured review meetings

05 AI for automotive workflows

AI integrated into your professional engineering workflow the way it actually should be: BYOK, on-prem, optional, auditable. No vendor cloud roundtrips. No leaked architecture diagrams. Real productivity in the tasks engineers actually do.

What we do

  • BYOK LLM integration with your Azure OpenAI, AWS Bedrock, or self-hosted endpoint
  • ASPICE-compatible AI workflow design (auditable AI assist, not a black box)
  • Code review automation, doc generation, requirements synthesis, test scaffolding
  • RAG over your internal architecture, history, and engineering standards
  • AI assistance designed around ISO 26262 and ISO 21434 evidence requirements
  • MISRA-aware code suggestions; LLM outputs gated through the same static analysis your engineers use, so no AI-generated code reaches production without clearing the same bar as hand-written code
  • Professional engineering team training on practical AI use without security or process drift

06 Embedded engineering

When you need senior embedded engineers on a hard problem. Our industry experts have done ECU bring-up, bare-metal debugging, RTOS porting, driver development, and BSP work across the platforms that show up in real automotive ECUs. Production code, MISRA-grade by default.

What we do

  • BSP development and customization across major automotive MCU families (NXP S32, Infineon AURIX, Renesas R-Car, TI Jacinto)
  • RTOS porting and configuration (FreeRTOS, AUTOSAR OS, QNX, INTEGRITY)
  • ECU bring-up and board bring-up for new hardware: from power-on to first signed image
  • Bare-metal driver development when the chip vendor's drivers fall short
  • Memory-constrained optimization and footprint reduction for production ECUs
  • MISRA C / MISRA C++ compliant production code; static analysis clean by default, on hand-written and generated code paths alike
  • Debug-from-scope investigations on integration issues no one else can find

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Email [email protected]